<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2258646</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Tue Dec 25 20:11:47 2018</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2018.2 (64-bit)</TD>
  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>228d108ede264a4f947f16b6ec205fbf</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>7</TD>
  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>d8a49a1926f15847a19a9cebfca6e759</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>d8a49a1926f15847a19a9cebfca6e759</TD>
  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7a100t</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>artix7</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>csg324</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i5-5200U CPU @ 2.20GHz</TD>
  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2195 MHz</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Microsoft Windows 8 or later , 64-bit</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>8.000 GB</TD>
  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>gui_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>addsrcwizard_specify_hdl_netlist_block_design=2</TD>
   <TD>addsrcwizard_specify_or_create_constraint_files=1</TD>
   <TD>addsrcwizard_specify_simulation_specific_hdl_files=2</TD>
   <TD>basedialog_cancel=10</TD>
</TR><TR ALIGN='LEFT'>   <TD>basedialog_ok=28</TD>
   <TD>cmdmsgdialog_ok=4</TD>
   <TD>commandsinput_type_tcl_command_here=4</TD>
   <TD>commonoptionschooserpanel_specify_generics_parameters=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>constraintschooserpanel_add_files=2</TD>
   <TD>coretreetablepanel_core_tree_table=3</TD>
   <TD>createsrcfiledialog_file_name=1</TD>
   <TD>filesetpanel_file_set_panel_tree=178</TD>
</TR><TR ALIGN='LEFT'>   <TD>flownavigatortreepanel_flow_navigator_tree=39</TD>
   <TD>graphicalview_zoom_in=6</TD>
   <TD>graphicalview_zoom_out=15</TD>
   <TD>mainmenumgr_edit=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_file=2</TD>
   <TD>mainmenumgr_flow=2</TD>
   <TD>mainmenumgr_project=1</TD>
   <TD>mainmenumgr_tools=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>msgtreepanel_message_view_tree=2</TD>
   <TD>openfileaction_cancel=1</TD>
   <TD>pacommandnames_add_sources=1</TD>
   <TD>pacommandnames_auto_connect_target=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_auto_update_hier=1</TD>
   <TD>pacommandnames_open_hardware_manager=4</TD>
   <TD>pacommandnames_set_used_in_prop=1</TD>
   <TD>pacommandnames_simulation_run_behavioral=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_src_disable=4</TD>
   <TD>paviews_code=6</TD>
   <TD>paviews_ip_catalog=1</TD>
   <TD>paviews_schematic=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>programdebugtab_open_target=2</TD>
   <TD>programdebugtab_program_device=8</TD>
   <TD>programfpgadialog_program=8</TD>
   <TD>progressdialog_background=7</TD>
</TR><TR ALIGN='LEFT'>   <TD>projectsettingssimulationpanel_tabbed_pane=11</TD>
   <TD>rdicommands_custom_commands=1</TD>
   <TD>rdicommands_delete=15</TD>
   <TD>rdicommands_settings=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>rdiviews_waveform_viewer=35</TD>
   <TD>removesourcesdialog_also_delete=3</TD>
   <TD>rungadget_show_error_and_critical_warning_messages=1</TD>
   <TD>schematicview_previous=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>settingsdialog_project_tree=5</TD>
   <TD>simpleoutputproductdialog_generate_output_products_immediately=3</TD>
   <TD>simulationobjectspanel_simulation_objects_tree_table=36</TD>
   <TD>simulationscopespanel_simulate_scope_table=8</TD>
</TR><TR ALIGN='LEFT'>   <TD>srcchooserpanel_add_directories=2</TD>
   <TD>srcchooserpanel_add_hdl_and_netlist_files_to_your_project=10</TD>
   <TD>srcchooserpanel_add_sources_from_subdirectories=1</TD>
   <TD>srcchooserpanel_create_file=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>srcmenu_ip_hierarchy=2</TD>
   <TD>syntheticagettingstartedview_recent_projects=3</TD>
   <TD>syntheticastatemonitor_cancel=1</TD>
   <TD>waveformnametree_waveform_name_tree=11</TD>
</TR><TR ALIGN='LEFT'>   <TD>xpg_coefilewidgdet_browse=1</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>addsources=12</TD>
   <TD>autoconnecttarget=2</TD>
   <TD>coreview=2</TD>
   <TD>customizecore=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>editdelete=15</TD>
   <TD>launchprogramfpga=8</TD>
   <TD>openhardwaremanager=4</TD>
   <TD>recustomizecore=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>runbitgen=12</TD>
   <TD>runschematic=1</TD>
   <TD>savefileproxyhandler=1</TD>
   <TD>setsourceenabled=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>showview=4</TD>
   <TD>simulationrun=3</TD>
   <TD>toolssettings=2</TD>
   <TD>viewtaskprojectmanager=6</TD>
</TR>  </TABLE>
</TR><TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>guimode=4</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>constraintsetcount=1</TD>
   <TD>core_container=false</TD>
   <TD>currentimplrun=impl_1</TD>
   <TD>currentsynthesisrun=synth_1</TD>
</TR><TR ALIGN='LEFT'>   <TD>default_library=xil_defaultlib</TD>
   <TD>designmode=RTL</TD>
   <TD>export_simulation_activehdl=8</TD>
   <TD>export_simulation_ies=8</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_modelsim=8</TD>
   <TD>export_simulation_questa=8</TD>
   <TD>export_simulation_riviera=8</TD>
   <TD>export_simulation_vcs=8</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_xsim=8</TD>
   <TD>implstrategy=Vivado Implementation Defaults</TD>
   <TD>launch_simulation_activehdl=0</TD>
   <TD>launch_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_modelsim=0</TD>
   <TD>launch_simulation_questa=0</TD>
   <TD>launch_simulation_riviera=0</TD>
   <TD>launch_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_xsim=2</TD>
   <TD>simulator_language=Verilog</TD>
   <TD>srcsetcount=39</TD>
   <TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
</TR><TR ALIGN='LEFT'>   <TD>target_language=Verilog</TD>
   <TD>target_simulator=XSim</TD>
   <TD>totalimplruns=2</TD>
   <TD>totalsynthesisruns=2</TD>
</TR>  </TABLE>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=11</TD>
    <TD>bufh=1</TD>
    <TD>carry4=405</TD>
    <TD>dsp48e1=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdce=402</TD>
    <TD>fdpe=97</TD>
    <TD>fdre=5126</TD>
    <TD>fdse=139</TD>
</TR><TR ALIGN='LEFT'>    <TD>gnd=92</TD>
    <TD>ibuf=19</TD>
    <TD>ibuf_intermdisable=16</TD>
    <TD>ibufds_intermdisable_int=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>idelayctrl=1</TD>
    <TD>idelaye2=16</TD>
    <TD>in_fifo=2</TD>
    <TD>inv=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>iserdese2=16</TD>
    <TD>ldce=171</TD>
    <TD>lut1=584</TD>
    <TD>lut2=1161</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut3=1266</TD>
    <TD>lut4=1164</TD>
    <TD>lut5=1350</TD>
    <TD>lut6=2506</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv=3</TD>
    <TD>muxf7=1203</TD>
    <TD>muxf8=480</TD>
    <TD>obuf=47</TD>
</TR><TR ALIGN='LEFT'>    <TD>obufds=2</TD>
    <TD>obuft=31</TD>
    <TD>obuftds=4</TD>
    <TD>oddr=5</TD>
</TR><TR ALIGN='LEFT'>    <TD>oserdese2=42</TD>
    <TD>out_fifo=4</TD>
    <TD>phaser_in_phy=2</TD>
    <TD>phaser_out_phy=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>phaser_ref=1</TD>
    <TD>phy_control=1</TD>
    <TD>plle2_adv=1</TD>
    <TD>ramd32=624</TD>
</TR><TR ALIGN='LEFT'>    <TD>rams32=208</TD>
    <TD>rams64e=1792</TD>
    <TD>srl16e=17</TD>
    <TD>srlc32e=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcc=89</TD>
    <TD>xadc=1</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=11</TD>
    <TD>bufh=1</TD>
    <TD>carry4=405</TD>
    <TD>dsp48e1=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdce=402</TD>
    <TD>fdpe=97</TD>
    <TD>fdre=5126</TD>
    <TD>fdse=139</TD>
</TR><TR ALIGN='LEFT'>    <TD>gnd=92</TD>
    <TD>ibuf=21</TD>
    <TD>idelayctrl=1</TD>
    <TD>idelaye2=16</TD>
</TR><TR ALIGN='LEFT'>    <TD>in_fifo=2</TD>
    <TD>iobuf_intermdisable=16</TD>
    <TD>iobufds_intermdisable=2</TD>
    <TD>iserdese2=16</TD>
</TR><TR ALIGN='LEFT'>    <TD>ldce=171</TD>
    <TD>lut1=584</TD>
    <TD>lut2=1161</TD>
    <TD>lut3=1266</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut4=1164</TD>
    <TD>lut5=1350</TD>
    <TD>lut6=2506</TD>
    <TD>mmcme2_adv=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>muxf7=307</TD>
    <TD>muxf8=32</TD>
    <TD>obuf=47</TD>
    <TD>obufds=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>obuft=15</TD>
    <TD>oddr=5</TD>
    <TD>oserdese2=42</TD>
    <TD>out_fifo=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>phaser_in_phy=2</TD>
    <TD>phaser_out_phy=4</TD>
    <TD>phaser_ref=1</TD>
    <TD>phy_control=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>plle2_adv=1</TD>
    <TD>ram256x1s=448</TD>
    <TD>ram32m=104</TD>
    <TD>srl16e=17</TD>
</TR><TR ALIGN='LEFT'>    <TD>srlc32e=1</TD>
    <TD>vcc=89</TD>
    <TD>xadc=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>ip_statistics</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clk_wiz_v6_0_1_0_0/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>clkin1_period=10.000</TD>
    <TD>clkin2_period=10.000</TD>
    <TD>clock_mgr_type=NA</TD>
    <TD>component_name=clk_wiz_0</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>enable_axi=0</TD>
    <TD>feedback_source=FDBK_AUTO</TD>
    <TD>feedback_type=SINGLE</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
    <TD>manual_override=false</TD>
    <TD>num_out_clk=1</TD>
    <TD>primitive=MMCM</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_dyn_phase_shift=false</TD>
    <TD>use_dyn_reconfig=false</TD>
    <TD>use_inclk_stopped=false</TD>
    <TD>use_inclk_switchover=false</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_locked=false</TD>
    <TD>use_max_i_jitter=false</TD>
    <TD>use_min_o_jitter=false</TD>
    <TD>use_phase_alignment=true</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_power_down=false</TD>
    <TD>use_reset=false</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clk_wiz_v6_0_1_0_0/2</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>clkin1_period=10.000</TD>
    <TD>clkin2_period=10.000</TD>
    <TD>clock_mgr_type=NA</TD>
    <TD>component_name=clk_wiz_for_cpu</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>enable_axi=0</TD>
    <TD>feedback_source=FDBK_AUTO</TD>
    <TD>feedback_type=SINGLE</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
    <TD>manual_override=false</TD>
    <TD>num_out_clk=1</TD>
    <TD>primitive=MMCM</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_dyn_phase_shift=false</TD>
    <TD>use_dyn_reconfig=false</TD>
    <TD>use_inclk_stopped=false</TD>
    <TD>use_inclk_switchover=false</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_locked=false</TD>
    <TD>use_max_i_jitter=false</TD>
    <TD>use_min_o_jitter=false</TD>
    <TD>use_phase_alignment=true</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_power_down=false</TD>
    <TD>use_reset=false</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dist_mem_gen_v8_0_12/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_addr_width=11</TD>
    <TD>c_default_data=0</TD>
    <TD>c_depth=2048</TD>
    <TD>c_elaboration_dir=./</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_family=artix7</TD>
    <TD>c_has_clk=1</TD>
    <TD>c_has_d=1</TD>
    <TD>c_has_dpo=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_dpra=0</TD>
    <TD>c_has_i_ce=0</TD>
    <TD>c_has_qdpo=0</TD>
    <TD>c_has_qdpo_ce=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_qdpo_clk=0</TD>
    <TD>c_has_qdpo_rst=0</TD>
    <TD>c_has_qdpo_srst=0</TD>
    <TD>c_has_qspo=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_qspo_ce=0</TD>
    <TD>c_has_qspo_rst=0</TD>
    <TD>c_has_qspo_srst=0</TD>
    <TD>c_has_spo=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_we=1</TD>
    <TD>c_mem_init_file=no_coe_file_loaded</TD>
    <TD>c_mem_type=1</TD>
    <TD>c_parser_type=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_pipeline_stages=0</TD>
    <TD>c_qce_joined=0</TD>
    <TD>c_qualify_we=0</TD>
    <TD>c_read_mif=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_reg_a_d_inputs=0</TD>
    <TD>c_reg_dpra_input=0</TD>
    <TD>c_sync_enable=1</TD>
    <TD>c_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=false</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=12</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=dist_mem_gen</TD>
    <TD>x_ipproduct=Vivado 2018.2</TD>
    <TD>x_ipsimlanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=8.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dist_mem_gen_v8_0_12/2</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_addr_width=9</TD>
    <TD>c_default_data=0</TD>
    <TD>c_depth=512</TD>
    <TD>c_elaboration_dir=./</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_family=artix7</TD>
    <TD>c_has_clk=1</TD>
    <TD>c_has_d=1</TD>
    <TD>c_has_dpo=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_dpra=0</TD>
    <TD>c_has_i_ce=0</TD>
    <TD>c_has_qdpo=0</TD>
    <TD>c_has_qdpo_ce=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_qdpo_clk=0</TD>
    <TD>c_has_qdpo_rst=0</TD>
    <TD>c_has_qdpo_srst=0</TD>
    <TD>c_has_qspo=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_qspo_ce=0</TD>
    <TD>c_has_qspo_rst=0</TD>
    <TD>c_has_qspo_srst=0</TD>
    <TD>c_has_spo=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_we=1</TD>
    <TD>c_mem_init_file=no_coe_file_loaded</TD>
    <TD>c_mem_type=1</TD>
    <TD>c_parser_type=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_pipeline_stages=0</TD>
    <TD>c_qce_joined=0</TD>
    <TD>c_qualify_we=0</TD>
    <TD>c_read_mif=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_reg_a_d_inputs=0</TD>
    <TD>c_reg_dpra_input=0</TD>
    <TD>c_sync_enable=1</TD>
    <TD>c_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=false</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=12</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=dist_mem_gen</TD>
    <TD>x_ipproduct=Vivado 2018.2</TD>
    <TD>x_ipsimlanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=8.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>mig_7series_v4_1/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>axi_enable=0</TD>
    <TD>burst_mode=8</TD>
    <TD>burst_type=SEQ</TD>
    <TD>clk_period=3077</TD>
</TR><TR ALIGN='LEFT'>    <TD>clkin_period=10000</TD>
    <TD>core_container=NA</TD>
    <TD>data_mask=1</TD>
    <TD>debug_port=OFF</TD>
</TR><TR ALIGN='LEFT'>    <TD>dq_width=16</TD>
    <TD>ecc=OFF</TD>
    <TD>interface_type=DDR2</TD>
    <TD>internal_vref=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
    <TD>language=Verilog</TD>
    <TD>level=CONTROLLER</TD>
    <TD>memory_address_map=BANK_ROW_COLUMN</TD>
</TR><TR ALIGN='LEFT'>    <TD>memory_part=mt47h64m16hr-25e</TD>
    <TD>memory_type=COMP</TD>
    <TD>no_of_controllers=1</TD>
    <TD>ordering=STRICT</TD>
</TR><TR ALIGN='LEFT'>    <TD>output_drv=HIGH</TD>
    <TD>phy_ratio=4</TD>
    <TD>refclk_freq=200</TD>
    <TD>refclk_type=NO_BUFFER</TD>
</TR><TR ALIGN='LEFT'>    <TD>rtt_nom=50</TD>
    <TD>synthesis_tool=Vivado</TD>
    <TD>sysclk_type=NO_BUFFER</TD>
    <TD>use_cs_port=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_odt_port=1</TD>
    <TD>vccaux_io=1.8V</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-internal=default::[not_specified]</TD>
    <TD>-internal_only=default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-name=default::[not_specified]</TD>
    <TD>-no_waivers=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
    <TD>-ruledecks=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-upgrade_cw=default::[not_specified]</TD>
    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>cfgbvs-1=1</TD>
    <TD>dpop-1=4</TD>
    <TD>dpop-2=4</TD>
    <TD>pdrc-153=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>reqp-1709=1</TD>
    <TD>rpbf-3=4</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_methodology</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>lutar-1=3</TD>
    <TD>pdrc-190=12</TD>
    <TD>reqp-1959=16</TD>
    <TD>synth-10=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>synth-5=128</TD>
    <TD>timing-17=1000</TD>
    <TD>timing-20=171</TD>
    <TD>timing-27=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>xdcb-5=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_power</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-advisory=default::[not_specified]</TD>
    <TD>-append=default::[not_specified]</TD>
    <TD>-file=[specified]</TD>
    <TD>-format=default::text</TD>
</TR><TR ALIGN='LEFT'>    <TD>-hier=default::power</TD>
    <TD>-l=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-no_propagation=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-return_string=default::[not_specified]</TD>
    <TD>-rpx=[specified]</TD>
    <TD>-verbose=default::[not_specified]</TD>
    <TD>-vid=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-xpe=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>airflow=250 (LFM)</TD>
    <TD>ambient_temp=25.0 (C)</TD>
    <TD>bi-dir_toggle=12.500000</TD>
    <TD>bidir_output_enable=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>board_layers=12to15 (12 to 15 Layers)</TD>
    <TD>board_selection=medium (10&quot;x10&quot;)</TD>
    <TD>clocks=0.008857</TD>
    <TD>confidence_level_clock_activity=Low</TD>
</TR><TR ALIGN='LEFT'>    <TD>confidence_level_design_state=High</TD>
    <TD>confidence_level_device_models=High</TD>
    <TD>confidence_level_internal_activity=Medium</TD>
    <TD>confidence_level_io_activity=Low</TD>
</TR><TR ALIGN='LEFT'>    <TD>confidence_level_overall=Low</TD>
    <TD>customer=TBD</TD>
    <TD>customer_class=TBD</TD>
    <TD>devstatic=0.107546</TD>
</TR><TR ALIGN='LEFT'>    <TD>die=xc7a100tcsg324-1</TD>
    <TD>dsp=0.000000</TD>
    <TD>dsp_output_toggle=12.500000</TD>
    <TD>dynamic=0.956929</TD>
</TR><TR ALIGN='LEFT'>    <TD>effective_thetaja=4.6</TD>
    <TD>enable_probability=0.990000</TD>
    <TD>family=artix7</TD>
    <TD>ff_toggle=12.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>flow_state=routed</TD>
    <TD>heatsink=medium (Medium Profile)</TD>
    <TD>i/o=0.513182</TD>
    <TD>input_toggle=12.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>junction_temp=29.9 (C)</TD>
    <TD>logic=0.015764</TD>
    <TD>mgtavcc_dynamic_current=0.000000</TD>
    <TD>mgtavcc_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavcc_total_current=0.000000</TD>
    <TD>mgtavcc_voltage=1.000000</TD>
    <TD>mgtavtt_dynamic_current=0.000000</TD>
    <TD>mgtavtt_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavtt_total_current=0.000000</TD>
    <TD>mgtavtt_voltage=1.200000</TD>
    <TD>mmcm=0.273751</TD>
    <TD>netlist_net_matched=NA</TD>
</TR><TR ALIGN='LEFT'>    <TD>off-chip_power=0.632684</TD>
    <TD>on-chip_power=1.064475</TD>
    <TD>output_enable=1.000000</TD>
    <TD>output_load=5.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>output_toggle=12.500000</TD>
    <TD>package=csg324</TD>
    <TD>pct_clock_constrained=15.000000</TD>
    <TD>pct_inputs_defined=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>phaser=0.010116</TD>
    <TD>platform=nt64</TD>
    <TD>pll=0.109154</TD>
    <TD>process=typical</TD>
</TR><TR ALIGN='LEFT'>    <TD>ram_enable=50.000000</TD>
    <TD>ram_write=50.000000</TD>
    <TD>read_saif=False</TD>
    <TD>set/reset_probability=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>signal_rate=False</TD>
    <TD>signals=0.022224</TD>
    <TD>simulation_file=None</TD>
    <TD>speedgrade=-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>static_prob=False</TD>
    <TD>temp_grade=commercial</TD>
    <TD>thetajb=5.7 (C/W)</TD>
    <TD>thetasa=4.6 (C/W)</TD>
</TR><TR ALIGN='LEFT'>    <TD>toggle_rate=False</TD>
    <TD>user_board_temp=25.0 (C)</TD>
    <TD>user_effective_thetaja=4.6</TD>
    <TD>user_junc_temp=29.9 (C)</TD>
</TR><TR ALIGN='LEFT'>    <TD>user_thetajb=5.7 (C/W)</TD>
    <TD>user_thetasa=4.6 (C/W)</TD>
    <TD>vccadc_dynamic_current=0.001600</TD>
    <TD>vccadc_static_current=0.020000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccadc_total_current=0.021600</TD>
    <TD>vccadc_voltage=1.800000</TD>
    <TD>vccaux_dynamic_current=0.257743</TD>
    <TD>vccaux_io_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_io_static_current=0.000000</TD>
    <TD>vccaux_io_total_current=0.000000</TD>
    <TD>vccaux_io_voltage=1.800000</TD>
    <TD>vccaux_static_current=0.018382</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_total_current=0.276125</TD>
    <TD>vccaux_voltage=1.800000</TD>
    <TD>vccbram_dynamic_current=0.000000</TD>
    <TD>vccbram_static_current=0.000294</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccbram_total_current=0.000294</TD>
    <TD>vccbram_voltage=1.000000</TD>
    <TD>vccint_dynamic_current=0.058400</TD>
    <TD>vccint_static_current=0.017765</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccint_total_current=0.076165</TD>
    <TD>vccint_voltage=1.000000</TD>
    <TD>vcco12_dynamic_current=0.000000</TD>
    <TD>vcco12_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco12_total_current=0.000000</TD>
    <TD>vcco12_voltage=1.200000</TD>
    <TD>vcco135_dynamic_current=0.000000</TD>
    <TD>vcco135_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco135_total_current=0.000000</TD>
    <TD>vcco135_voltage=1.350000</TD>
    <TD>vcco15_dynamic_current=0.000000</TD>
    <TD>vcco15_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco15_total_current=0.000000</TD>
    <TD>vcco15_voltage=1.500000</TD>
    <TD>vcco18_dynamic_current=0.575315</TD>
    <TD>vcco18_static_current=0.004000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco18_total_current=0.579315</TD>
    <TD>vcco18_voltage=1.800000</TD>
    <TD>vcco25_dynamic_current=0.000000</TD>
    <TD>vcco25_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco25_total_current=0.000000</TD>
    <TD>vcco25_voltage=2.500000</TD>
    <TD>vcco33_dynamic_current=0.008736</TD>
    <TD>vcco33_static_current=0.004000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco33_total_current=0.012736</TD>
    <TD>vcco33_voltage=3.300000</TD>
    <TD>version=2018.2</TD>
    <TD>xadc=0.003880</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufgctrl_available=32</TD>
    <TD>bufgctrl_fixed=0</TD>
    <TD>bufgctrl_used=10</TD>
    <TD>bufgctrl_util_percentage=31.25</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufhce_available=96</TD>
    <TD>bufhce_fixed=0</TD>
    <TD>bufhce_used=1</TD>
    <TD>bufhce_util_percentage=1.04</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufio_available=24</TD>
    <TD>bufio_fixed=0</TD>
    <TD>bufio_used=0</TD>
    <TD>bufio_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufmrce_available=12</TD>
    <TD>bufmrce_fixed=0</TD>
    <TD>bufmrce_used=0</TD>
    <TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufr_available=24</TD>
    <TD>bufr_fixed=0</TD>
    <TD>bufr_used=0</TD>
    <TD>bufr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_available=6</TD>
    <TD>mmcme2_adv_fixed=1</TD>
    <TD>mmcme2_adv_used=3</TD>
    <TD>mmcme2_adv_util_percentage=50.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>plle2_adv_available=6</TD>
    <TD>plle2_adv_fixed=1</TD>
    <TD>plle2_adv_used=1</TD>
    <TD>plle2_adv_util_percentage=16.67</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>dsp48e1_only_used=4</TD>
    <TD>dsps_available=240</TD>
    <TD>dsps_fixed=0</TD>
    <TD>dsps_used=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>dsps_util_percentage=1.67</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>blvds_25=0</TD>
    <TD>diff_hstl_i=0</TD>
    <TD>diff_hstl_i_18=0</TD>
    <TD>diff_hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_ii_18=0</TD>
    <TD>diff_hsul_12=0</TD>
    <TD>diff_mobile_ddr=0</TD>
    <TD>diff_sstl135=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl135_r=0</TD>
    <TD>diff_sstl15=0</TD>
    <TD>diff_sstl15_r=0</TD>
    <TD>diff_sstl18_i=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl18_ii=1</TD>
    <TD>hstl_i=0</TD>
    <TD>hstl_i_18=0</TD>
    <TD>hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>hstl_ii_18=0</TD>
    <TD>hsul_12=0</TD>
    <TD>lvcmos12=0</TD>
    <TD>lvcmos15=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvcmos18=1</TD>
    <TD>lvcmos25=0</TD>
    <TD>lvcmos33=1</TD>
    <TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvttl=0</TD>
    <TD>mini_lvds_25=0</TD>
    <TD>mobile_ddr=0</TD>
    <TD>pci33_3=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ppds_25=0</TD>
    <TD>rsds_25=0</TD>
    <TD>sstl135=0</TD>
    <TD>sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>sstl15=0</TD>
    <TD>sstl15_r=0</TD>
    <TD>sstl18_i=0</TD>
    <TD>sstl18_ii=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>tmds_33=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>block_ram_tile_available=135</TD>
    <TD>block_ram_tile_fixed=0</TD>
    <TD>block_ram_tile_used=0</TD>
    <TD>block_ram_tile_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18_available=270</TD>
    <TD>ramb18_fixed=0</TD>
    <TD>ramb18_used=0</TD>
    <TD>ramb18_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36_fifo_available=135</TD>
    <TD>ramb36_fifo_fixed=0</TD>
    <TD>ramb36_fifo_used=0</TD>
    <TD>ramb36_fifo_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg_functional_category=Clock</TD>
    <TD>bufg_used=10</TD>
    <TD>bufh_functional_category=Clock</TD>
    <TD>bufh_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>carry4_functional_category=CarryLogic</TD>
    <TD>carry4_used=405</TD>
    <TD>dsp48e1_functional_category=Block Arithmetic</TD>
    <TD>dsp48e1_used=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdce_functional_category=Flop &amp; Latch</TD>
    <TD>fdce_used=402</TD>
    <TD>fdpe_functional_category=Flop &amp; Latch</TD>
    <TD>fdpe_used=71</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre_functional_category=Flop &amp; Latch</TD>
    <TD>fdre_used=4862</TD>
    <TD>fdse_functional_category=Flop &amp; Latch</TD>
    <TD>fdse_used=121</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibuf_functional_category=IO</TD>
    <TD>ibuf_intermdisable_functional_category=IO</TD>
    <TD>ibuf_intermdisable_used=16</TD>
    <TD>ibuf_used=19</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibufds_intermdisable_int_functional_category=IO</TD>
    <TD>ibufds_intermdisable_int_used=4</TD>
    <TD>idelayctrl_functional_category=IO</TD>
    <TD>idelayctrl_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>idelaye2_functional_category=IO</TD>
    <TD>idelaye2_used=16</TD>
    <TD>in_fifo_functional_category=IO</TD>
    <TD>in_fifo_used=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>inv_functional_category=LUT</TD>
    <TD>inv_used=3</TD>
    <TD>iserdese2_functional_category=IO</TD>
    <TD>iserdese2_used=16</TD>
</TR><TR ALIGN='LEFT'>    <TD>ldce_functional_category=Flop &amp; Latch</TD>
    <TD>ldce_used=171</TD>
    <TD>lut1_functional_category=LUT</TD>
    <TD>lut1_used=538</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut2_functional_category=LUT</TD>
    <TD>lut2_used=1154</TD>
    <TD>lut3_functional_category=LUT</TD>
    <TD>lut3_used=1146</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut4_functional_category=LUT</TD>
    <TD>lut4_used=1162</TD>
    <TD>lut5_functional_category=LUT</TD>
    <TD>lut5_used=1325</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut6_functional_category=LUT</TD>
    <TD>lut6_used=2467</TD>
    <TD>mmcme2_adv_functional_category=Clock</TD>
    <TD>mmcme2_adv_used=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>muxf7_functional_category=MuxFx</TD>
    <TD>muxf7_used=1203</TD>
    <TD>muxf8_functional_category=MuxFx</TD>
    <TD>muxf8_used=480</TD>
</TR><TR ALIGN='LEFT'>    <TD>obuf_functional_category=IO</TD>
    <TD>obuf_used=47</TD>
    <TD>obufds_functional_category=IO</TD>
    <TD>obufds_used=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>obuft_functional_category=IO</TD>
    <TD>obuft_used=31</TD>
    <TD>obuftds_functional_category=IO</TD>
    <TD>obuftds_used=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>oddr_functional_category=IO</TD>
    <TD>oddr_used=5</TD>
    <TD>oserdese2_functional_category=IO</TD>
    <TD>oserdese2_used=42</TD>
</TR><TR ALIGN='LEFT'>    <TD>out_fifo_functional_category=IO</TD>
    <TD>out_fifo_used=4</TD>
    <TD>phaser_in_phy_functional_category=IO</TD>
    <TD>phaser_in_phy_used=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>phaser_out_phy_functional_category=IO</TD>
    <TD>phaser_out_phy_used=4</TD>
    <TD>phaser_ref_functional_category=IO</TD>
    <TD>phaser_ref_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>phy_control_functional_category=IO</TD>
    <TD>phy_control_used=1</TD>
    <TD>plle2_adv_functional_category=Clock</TD>
    <TD>plle2_adv_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramd32_functional_category=Distributed Memory</TD>
    <TD>ramd32_used=624</TD>
    <TD>rams32_functional_category=Distributed Memory</TD>
    <TD>rams32_used=208</TD>
</TR><TR ALIGN='LEFT'>    <TD>rams64e_functional_category=Distributed Memory</TD>
    <TD>rams64e_used=1792</TD>
    <TD>srl16e_functional_category=Distributed Memory</TD>
    <TD>srl16e_used=18</TD>
</TR><TR ALIGN='LEFT'>    <TD>xadc_functional_category=Others</TD>
    <TD>xadc_used=1</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>f7_muxes_available=31700</TD>
    <TD>f7_muxes_fixed=0</TD>
    <TD>f7_muxes_used=1203</TD>
    <TD>f7_muxes_util_percentage=3.79</TD>
</TR><TR ALIGN='LEFT'>    <TD>f8_muxes_available=15850</TD>
    <TD>f8_muxes_fixed=0</TD>
    <TD>f8_muxes_used=480</TD>
    <TD>f8_muxes_util_percentage=3.03</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=2208</TD>
    <TD>lut_as_logic_available=63400</TD>
    <TD>lut_as_logic_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_used=6613</TD>
    <TD>lut_as_logic_util_percentage=10.43</TD>
    <TD>lut_as_memory_available=19000</TD>
    <TD>lut_as_memory_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_used=2226</TD>
    <TD>lut_as_memory_util_percentage=11.72</TD>
    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=18</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_available=126800</TD>
    <TD>register_as_flip_flop_fixed=0</TD>
    <TD>register_as_flip_flop_used=5456</TD>
    <TD>register_as_flip_flop_util_percentage=4.30</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_latch_available=126800</TD>
    <TD>register_as_latch_fixed=0</TD>
    <TD>register_as_latch_used=171</TD>
    <TD>register_as_latch_util_percentage=0.13</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_luts_available=63400</TD>
    <TD>slice_luts_fixed=0</TD>
    <TD>slice_luts_used=8839</TD>
    <TD>slice_luts_util_percentage=13.94</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_available=126800</TD>
    <TD>slice_registers_fixed=0</TD>
    <TD>slice_registers_used=5627</TD>
    <TD>slice_registers_util_percentage=4.44</TD>
</TR><TR ALIGN='LEFT'>    <TD>fully_used_lut_ff_pairs_fixed=4.44</TD>
    <TD>fully_used_lut_ff_pairs_used=407</TD>
    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=2208</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_available=63400</TD>
    <TD>lut_as_logic_fixed=0</TD>
    <TD>lut_as_logic_used=6613</TD>
    <TD>lut_as_logic_util_percentage=10.43</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_available=19000</TD>
    <TD>lut_as_memory_fixed=0</TD>
    <TD>lut_as_memory_used=2226</TD>
    <TD>lut_as_memory_util_percentage=11.72</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=18</TD>
    <TD>lut_ff_pairs_with_one_unused_flip_flop_fixed=18</TD>
    <TD>lut_ff_pairs_with_one_unused_flip_flop_used=1566</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_ff_pairs_with_one_unused_lut_output_fixed=1566</TD>
    <TD>lut_ff_pairs_with_one_unused_lut_output_used=1624</TD>
    <TD>lut_flip_flop_pairs_available=63400</TD>
    <TD>lut_flip_flop_pairs_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_flip_flop_pairs_used=2210</TD>
    <TD>lut_flip_flop_pairs_util_percentage=3.49</TD>
    <TD>slice_available=15850</TD>
    <TD>slice_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_used=3209</TD>
    <TD>slice_util_percentage=20.25</TD>
    <TD>slicel_fixed=0</TD>
    <TD>slicel_used=2023</TD>
</TR><TR ALIGN='LEFT'>    <TD>slicem_fixed=0</TD>
    <TD>slicem_used=1186</TD>
    <TD>unique_control_sets_used=265</TD>
    <TD>using_o5_and_o6_fixed=265</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_and_o6_used=0</TD>
    <TD>using_o5_output_only_fixed=0</TD>
    <TD>using_o5_output_only_used=17</TD>
    <TD>using_o6_output_only_fixed=17</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o6_output_only_used=1</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bscane2_available=4</TD>
    <TD>bscane2_fixed=0</TD>
    <TD>bscane2_used=0</TD>
    <TD>bscane2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>capturee2_available=1</TD>
    <TD>capturee2_fixed=0</TD>
    <TD>capturee2_used=0</TD>
    <TD>capturee2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>dna_port_available=1</TD>
    <TD>dna_port_fixed=0</TD>
    <TD>dna_port_used=0</TD>
    <TD>dna_port_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>efuse_usr_available=1</TD>
    <TD>efuse_usr_fixed=0</TD>
    <TD>efuse_usr_used=0</TD>
    <TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_available=1</TD>
    <TD>frame_ecce2_fixed=0</TD>
    <TD>frame_ecce2_used=0</TD>
    <TD>frame_ecce2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>icape2_available=2</TD>
    <TD>icape2_fixed=0</TD>
    <TD>icape2_used=0</TD>
    <TD>icape2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcie_2_1_available=1</TD>
    <TD>pcie_2_1_fixed=0</TD>
    <TD>pcie_2_1_used=0</TD>
    <TD>pcie_2_1_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>startupe2_available=1</TD>
    <TD>startupe2_fixed=0</TD>
    <TD>startupe2_used=0</TD>
    <TD>startupe2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>xadc_available=1</TD>
    <TD>xadc_fixed=0</TD>
    <TD>xadc_used=1</TD>
    <TD>xadc_util_percentage=100.00</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>router</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>actual_expansions=9472912</TD>
    <TD>bogomips=0</TD>
    <TD>bram18=0</TD>
    <TD>bram36=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufg=0</TD>
    <TD>bufr=0</TD>
    <TD>congestion_level=0</TD>
    <TD>ctrls=265</TD>
</TR><TR ALIGN='LEFT'>    <TD>dsp=4</TD>
    <TD>effort=2</TD>
    <TD>estimated_expansions=11359434</TD>
    <TD>ff=5627</TD>
</TR><TR ALIGN='LEFT'>    <TD>global_clocks=10</TD>
    <TD>high_fanout_nets=22</TD>
    <TD>iob=103</TD>
    <TD>lut=9439</TD>
</TR><TR ALIGN='LEFT'>    <TD>movable_instances=18555</TD>
    <TD>nets=21881</TD>
    <TD>pins=120222</TD>
    <TD>pll=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>router_runtime=1.000000</TD>
    <TD>router_timing_driven=1</TD>
    <TD>threads=2</TD>
    <TD>timing_constraints_exist=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-assert=default::[not_specified]</TD>
    <TD>-bufg=default::12</TD>
    <TD>-cascade_dsp=default::auto</TD>
    <TD>-constrset=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-control_set_opt_threshold=default::auto</TD>
    <TD>-directive=default::default</TD>
    <TD>-fanout_limit=default::10000</TD>
    <TD>-flatten_hierarchy=default::rebuilt</TD>
</TR><TR ALIGN='LEFT'>    <TD>-fsm_extraction=default::auto</TD>
    <TD>-gated_clock_conversion=default::off</TD>
    <TD>-generic=default::[not_specified]</TD>
    <TD>-include_dirs=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-keep_equivalent_registers=default::[not_specified]</TD>
    <TD>-max_bram=default::-1</TD>
    <TD>-max_bram_cascade_height=default::-1</TD>
    <TD>-max_dsp=default::-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-max_uram=default::-1</TD>
    <TD>-max_uram_cascade_height=default::-1</TD>
    <TD>-mode=default::default</TD>
    <TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_lc=default::[not_specified]</TD>
    <TD>-no_srlextract=default::[not_specified]</TD>
    <TD>-no_timing_driven=default::[not_specified]</TD>
    <TD>-part=xc7a100tcsg324-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-resource_sharing=default::auto</TD>
    <TD>-retiming=default::[not_specified]</TD>
    <TD>-rtl=default::[not_specified]</TD>
    <TD>-rtl_skip_constraints=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-rtl_skip_ip=default::[not_specified]</TD>
    <TD>-seu_protect=default::none</TD>
    <TD>-sfcu=default::[not_specified]</TD>
    <TD>-shreg_min_size=default::3</TD>
</TR><TR ALIGN='LEFT'>    <TD>-top=SOPC</TD>
    <TD>-verilog_define=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>elapsed=00:01:37s</TD>
    <TD>hls_ip=0</TD>
    <TD>memory_gain=663.664MB</TD>
    <TD>memory_peak=984.301MB</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-sim_mode=default::behavioral</TD>
    <TD>-sim_type=default::</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
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